As background for our invention computer systems use arrays to store information and these arrays are sometimes subject to hardware errors: individual array cell, bitline, wordline, etc. When most large arrays are designed, they have redundant areas (typically bitlines or wordlines), that may be used to replace the normal functional areas of the array if a hardware error is found in them. However, previously these redundant areas have only been used during the chip manufacturing process to repair defects, typically by blowing fuses on the array to force the redundant cells to replace the defective cells. Estimates show that only about 10% of the time, the manufacturing process will have to utilize these redundant areas to produce a fully working chip.
In addition, typically arrays have a self-test apparatus built into them for testing the array: Array Built-In Self-Test (ABIST). This apparatus is typically used to test the array during the manufacturing process and when the computer system is powered-on at the customer's location.
For a background of our invention, reference to the application listed above, and to the discussion herein relating to our improved ABIST test and apparatus which enables us using the invention described herein to make use of redundant (or spare) cells that were not used in the manufacturing operation.
In general, during manufacturing of a computer system, integrated circuit arrays are tested by providing a known data input at a known address to the array and comparing the output to the expected output. One well-known and widely used prior art system for testing integrated circuit logic, particularly integrated circuit memory arrays, is to form a dedicated test circuit on the chip with the array itself. This is called Array Built-In Self Test (ABIST) logic.
An early example of ABIST technology, one that allowed elimination of an alternative microprocessor self test via a PLA LSSD test with I/O isolation of RAM functional test with no performance measurement, is represented by U.S. Pat. No. 4,841,485, granted Jun. 20, 1989 to R. J. Prilik et al, and assigned to International Business Machines Corp. This basic patent provided a memory array of bistable memory cells connectable to two different voltages that will operate when biased with both voltages at the same level in a bistable mode, and when biased at different voltage levels, will operating in an embedded self test binary pattern mode. The uses of this base technology also has been explored by others. Some related ABIST developments have been referenced above in the related pending applications of the assignee. There have been IBM Publications also relating to the area, including the IBM Journal of Research and Development article R. W. Bassett et al, "Boundary-Scann Design Principles for Efficient LSSD ASIC Testing, Vol. 34, No. 2/3 March/May 1990. Other IBM patents in the field include U.S. Pat. Nos. 5,442,641; 5,173,906 and 5,386,392.
With the many inventions in this field which have been made, this technology now allows high speed testing of the array without having to force correspondence between the array and the input/output connections to the chip itself.
U.S. Pat. No. 5,173,906 to Dreibelbis et al, issued Dec. 22, 1992, provides a BIST (Built-In Self Test) function for VLSI logic or memory module which is programmable. This circuitry is provided with a looping capability to enable enhanced burn-in testing. An on-chip test arrangement for VLSI circuits is provided with programmable data pattern sequences wherein the data patterns are selectable via instruction code in order to reduce the probability of self test redesign. However, this Dreibelbis patent does not provide flexibility to test VLSI circuits with any and all tests which can be required to test both static and dynamic arrays, in accordance with the invention claimed in U.S. Ser. No. 08/450,585 Filed May 31, 1995, by Turgeon et al, entitled "Programmable Built-In Self Test Method and Controller for Arrays". Generally, this prior application is our preferred ABIST embodiment for the present application representing an ABIST that has the programmable ability to test and identify defective array locations and using our invention to take corrective action.
In spite of the ABIST advancement for computer systems which use arrays to store information, there is a problem that our invention solves which is that if a defect is later found after the system had been shipped to the customer, there was no way to make use of these redundant cells that were never used during the manufacturing process. In fact, in some computer systems, if an array failed in the customer's location, it would not be possible to perform a power-on reset of the system, since the ABIST test of the defective array would not complete successfully.
While ABIST advancement has existed for some time, nevertheless the problem that a defect found after system shipment to a customer has likewise existed for some times. Several methods have been used in the past to solve this problem of array defects in the customer's location. Some recent computer systems used some form of line delete to remove bad sections of an array from use while the System is running. In large mainframes manufactured by IBM this information obtained during manufacturing had always been saved by the Service Processor, so it can be reloaded into the arrays at the next power-on reset. Therefore, if the self-test on the array fails, it can be ignored since there is information kept of all previous problems found and this information is reloaded to delete all previously defective locations. However, in more modern developments which provide reduced cost machines, constraint have been placed on the Service Processor which is unable to save the defective array location information for a later reload, because this defective array location information can not be kept in the Service Processor. Therefore, the only "safe" thing to do would be to not allow continued operation after an array self-test operation fails during power-on reset. This would provide a severe impact to customer availability. The power on reset would fail.
The IBM bi-polar mainframe known as the IBM series ES/9000-9021 implemented a mechanism called STAR (Self Test Address Relocation) in its level two cache that allows redundant array areas to replace defective array locations. However, it does not make use of a programmable ABIST utilized in our improved apparatus which we have described, but it used additional complex and expensive logic/state machines to automatically determine repair actions.
So, it is important problem in modern systems, to provide a reduced cost computer system that has no way to retain defective array location information after the manufacturing process is complete to be repaired at a customer location at power-on reset time. In fact, with modern systems, if the array fails at the customer's locations, it would not be possible, without our invention to perform a power-on reset of the system, since the ABIST test of the defective array would not complete successfully.